Are you a skilled CPU Design Verification Engineer looking for an exciting opportunity at Google? This could be your chance to join one of the tech industry’s leading companies in Bangalore. With a competitive salary of up to 12 Lakhs, this position offers a unique chance to work on cutting-edge projects and advance your career.
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About the Google
Google is an American multinational technology company focusing on artificial intelligence, online advertising, search engine technology, cloud computing, computer software, quantum computing, e-commerce, and consumer electronics. It has been referred to as “the most powerful company in the world” and as one of the world’s most valuable brands due to its market dominance, data collection, and technological advantages in artificial intelligence. Google’s parent company Alphabet Inc. is one of the five Big Tech companies, alongside Amazon, Apple, Meta, and Microsoft.
About the CPU Design Verification Engineer
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of the server chip design team, you will verify digital designs. You will also collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Eligibility Criteria
Bachelor’s degree in Electrical Engineering or equivalent practical experience.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at the RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, etc.).
Experience in scripting using Python, Perl, or shell scripts.
Preferred Qualification
Master’s degree in Electrical Engineering or Computer Science.
Experience with ARM Instruction Set architecture or processor microarchitecture.
Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Role and Responsibility
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Participate in reviews with architecture and design teams.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry-leading formal tools.
Participate in methodology improvements and other initiatives. Identify and write all types of coverage measures for stimulus and corner cases.
Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.
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Salary
₹12L – ₹34L
Note: Salary information is taken from here!
Location
India: Bangalore, Karnataka
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How To Apply?
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